This invention relates to operation of a memory having an FET memory cell accessed by a pair of complementary bit lines and, more particularly, to a circuit incorporating both bipolar transistors and field-effect transistors connected to the complementary bit lines for providing functions of writing, reading, and restoration of the bit-line voltage in response to a set of logic signals.
A memory for a digital computer or data processing equipment, such as a random-access memory, is composed of an array of memory cells, arranged typically in rows and columns, addressed by signals on word lines and bit lines. The bit lines of a column of cells serve as a common port by which the cells in the column are accessed for reading or writing via a common port. By way of example, the memory element of a cell may comprise a bistable flip-flop circuit wherein the state of the flip flop may be sensed for reading stored data and altered for writing new data, the sensing and the altering being accomplished, respectively, by a sensing of voltage and application of current to terminals of the common port.
In the case of a memory formed of a bank of memory cells, an individual one of the cells is addressed for the reading or writing of the cell. Due to the sharing of a common port by many cells, internal wiring of the memory provides for communication of signals between the cells of a column and the common port. There is a propagation delay during communication of the signal between an addressed cell and the port. The amount of delay can be reduced by reducing the physical size of the memory, as well as by restoring the voltage at each terminal of the common port to an equal value, and to a voltage level between those of a logic-1 signal and a logic-0 signal. This reduces the transient response in altering the logic state of the port upon the reading of new data from a memory cell, and thereby reduces the propagation delay.
In order to reduce the physical size of the memory, it is preferable to employ field-effect transistors (FETs) because the physical construction of an FET occupies less space than does the physical size of a bipolar transistor. However, the bipolar transistor has a faster dynamic response. Accordingly, in order to take advantage of both forms of transistors, it is advantageous to construct the semiconductor circuit for control of the memory by use of both bipolar transistors and FETs. Furthermore, in order to reduce the average power dissipation within the memory cell, so as to reduce cooling requirements and permit more dense packaging of the memory cells, complementary circuits of FETs may be employed, so called CMOS (complementary metal-oxide semiconductor) FETs. Complementary FET circuits have significant power flow only during a transition state of an FET, with virtually no power being expended during the remainder of the operating time of the FET circuit.
It is to be noted that the term MOS refers to a specific structure of an FET employing a metal oxide as was a common practice, and that today other forms of construction are also employed and may be preferred. Therefore, herein, only the terms FET (or field effect transistor) and bipolar transistors are used to describe the transistors of interest herein, and a circuit employing both kinds of transistors may be referred to as a BiFET circuit.
A problem arises that, in the use of both FETs and bipolar transistors in a circuit, the advantage of low power dissipation is lost to some extent because the current may flow in a bipolar transistor both during transitions in the current state of the transistor, as well as during operation of the transistor between the transitions in current state. Thus, the bipolar transistor is dissipating power continuously. As a result, in presently available circuitry, a compromise must be made between the enhanced dynamic response provided by a bipolar transistor and the disadvantageous increased power dissipation.